Semiconductor device and method for fabricating the same

ABSTRACT

A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substrate located between the gates as a seed layer, and formed to have a larger line-width than that of the second active area in a longitudinal direction of the gate.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.11/872,023, filed on Oct. 14, 2007, and claims priority from KoreanPatent Application No. 10-2007-0050788, filed on May 25, 2007, both ofwhich are incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

The present invention generally relates to a semiconductor device. Moreparticularly, the present invention relates to a semiconductorcomprising a fin-transistor and a method for fabricating the same.

In a fin-channel-array-transistor (“FCAT”), a channel width of finchannel transistors is determined by a short width of an active regionmask. That is, since a width of a gate is equal to the short width ofthe active region mask in a semiconductor device [e.g., Dynamic RandomAccess Memory (“DRAM”)], the fin channel transistor should not besmaller than a length between source/drains adjacent to a channel width.The fin channel transistor can reduce the short channel effects (“SCE”)as the channel width becomes smaller, by increasing the effectivechannel width. However, there is a limit to how much the channel widthof the fin channel transistor can be reduced because it is necessary tosecure an area for the source/drain contact regions.

Since a recess gate mask for forming a fin channel transistor has aline/space type pattern, a gate electrode formed over a device isolationstructure is separated from a storage node junction region by a gateinsulating film, thereby increasing a parasitic capacitance of the gateelectrode. The parasitic capacitance of the gate electrode degrades theoperation speed of the cell transistor. Also, leakage current isincreased in the storage node junction region due to a gate induceddrain leakage (“GIDL”) effect, thereby degrading refresh characteristicsof the DRAM.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the invention are directed to a fin gate in asemiconductor device. According to one embodiment, the fin gate isformed in a fin-type active region of a semiconductor device where theline width is smaller than the width of source/drains, thereby reducingshort channel effects.

According to one embodiment, a semiconductor device comprises an activeregion including a first active area to be a source/drain and a secondactive area to be a gate, and a device isolation region defining theactive region. The second active area is formed as a portion of a fingate, and the first active area is formed growing a semiconductorsubstrate between the neighboring gates as a seed layer. In alongitudinal direction of the gate, a line width of the first activearea is greater than the width of the second active area.

According to another embodiment, a method for fabricating asemiconductor device comprises: forming a device isolation structureover a semiconductor substrate to define an active region including afirst active area and a second active area, wherein the second activearea is formed as a portion of a fin gate, and the first active regionis formed growing the semiconductor substrate between two neighboringgates as a seed layer, wherein a line width of the first active regionis greater than the width of the second active region; etching a portionof the device isolation structure overlapping the gate by using a recessmask to form a recess; and forming the fin gate including a gateconductive layer to fill the recess.

In one embodiment, a method of fabricating a semiconductor device havinga fin gate includes forming first and second trenches on a semiconductorsubstrate to define a protruding portion between the first and secondtrenches; etching a portion of the protruding portion to define first,second, and third recesses, the first recess being adjacent to the firsttrench, the second recess being adjacent to the second trench, the thirdrecess being defined between the first and second recesses; andperforming a selective epitaxial process on the semiconductor substrateto grow semiconductor material at the first, second, and third recess toform a first active region.

In another embodiment, the method further includes forming a firstinsulation layer within the first and second trenches, the firstinsulation layer having an upper surface that is provided below an uppersurface of the protruding portion. The semiconductor material grown bythe epitaxial process extends partly over the first insulation layerprovided at the first and second trenches. The protruding portion isused to define the fin gate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout illustrating a semiconductor device according to anembodiment of the invention;

FIG. 2 is a cross-sectional view illustrating a semiconductor deviceaccording to an embodiment of the invention;

FIGS. 3 a through 3 h are cross-sectional views illustrating a methodfor fabricating a semiconductor device according to an embodiment of theinvention;

FIG. 4 is a cross-sectional view illustrating a method for fabricating asemiconductor device according to another embodiment of the invention;and

FIG. 5 is a layout illustrating a semiconductor device according toanother embodiment of the invention.

DESCRIPTION OF EMBODIMENTS

FIG. 1 is a layout illustrating a semiconductor device according to anembodiment of the invention. The semiconductor device comprises of anactive region 100 defined by a device isolation region 120, a fin gateregion 102, and a gate region 104. A fin transistor is formed in fingate region 102. Active region 100 includes a first active region 106that is to become source/drains and a second active region 108overlapping with a gate region 104. A longitudinal direction of gateregion 104 is defined as a “vertical direction”, and a longitudinaldirection of active region 100 is defined as a “horizontal direction”.Fin gate region 102 is formed in a line type, and overlaps with secondactive region 108. In the vertical direction, the line width of firstactive region 106 is F, and the line width of second region 108 is G(where 7F/20<G<19F/20 and F is a distance between the neighboring twogate regions). Gate region 102 is not limited to a line type. In anotherembodiment of the invention, a fin gate region 502 as shown in FIG. 5 isformed in an island type.

FIG. 2 is a cross-sectional view illustrating a semiconductor deviceaccording to an embodiment of the invention. FIG. 2( i) is across-sectional view taken along I-I′ of FIG. 1. FIG. 2( ii) is across-sectional view taken along II-II′ of FIG. 1. FIG. 2( iii) is across-sectional view taken along III-III′ FIG. 1. The semiconductordevice comprises a device isolation structure 220, a silicon epitaxialgrowth layer 230, a fin-type active region 238, and a fin gate structure280. Device isolation structure 220 defines an active region includingsilicon epitaxial growth layer 230. Fin gate structure 280 is disposedover fin-type active region 238.

A portion of a semiconductor substrate 210 of a first active region 106of FIG. 1 is selectively etched. A thermal treatment process isperformed on the selectively etched semiconductor substrate 210 as aseed layer, to form silicon epitaxial growth layer 230. A depth of theetched semiconductor substrate 210 is in a range of about 10 nm to 100nm. The thermal treatment process is performed under a H₂ atmosphere ata temperature in a range of about 500° C. to 1,000° C. A plasma cleaningprocess including SF₆/H₂ is performed on the etched semiconductorsubstrate 210. The plasma cleaning process and the thermal treatmentprocess are performed by an in-situ method.

Device isolation structure 220 is formed to have a stacked structurehaving a first device isolation insulating film 216 and a second deviceisolation insulating film 218. Fin gate structure 280 is formed to havea stacked structure having a lower gate electrode 252, an upper gateelectrode 262, and a gate hard mask layer 272 over a gate insulatingfilm 240.

FIGS. 3 a to 3 h are cross-sectional views illustrating a method forfabricating a semiconductor device according to an embodiment of theinvention. FIGS. 3 a(i) to 3 h(i) are cross-sectional views taken alongI-I′ of FIG. 1. FIGS. 3 a(ii) to 3 h(ii) are cross-sectional views takenalong II-II′ of FIG. 1. FIGS. 3 a(iii) to 3 h(iii) are cross-sectionalviews taken along III-III′ FIG. 1.

A pad insulating film 312 is formed over a semiconductor substrate 310.A portion of pad insulating film 312 and semiconductor substrate 310 areselectively etched using a device isolation mask (not shown) as anetching mask, to form a trench 314 that defines active region 100 ofFIG. 1. A first insulating film for device isolation 316 is formed tofill a portion of trench 314. In the vertical direction, a width of thedevice isolation mask becomes smaller so that a distance betweenneighboring active regions 100 becomes broader. As a result, adeposition margin of first insulating film for device isolation 316 canbe increased.

Referring to FIGS. 3 c and 3 d, pad insulating film 312 and a portion ofunderlying semiconductor substrate 310 in first active region 106 ofFIG. 1 are selectively etched to form a recess 322. A selectiveepitaxial process is performed on a surface of semiconductor substrate310 as a seed layer in the recess 322 to form a silicon epitaxial growthlayer 330. Pad insulating film 312 is disposed over semiconductorsubstrate 310 in second active region 108 of FIG. 1, so that siliconepitaxial growth layer 330 is not formed in second active region 108.Silicon epitaxial growth layer 330 is grown toward the upper surface andthe side surface of semiconductor substrate 310, so that, in thevertical direction, a width of first active region 106 may besubstantially equal to the distance F between the two neighboring gates.

A depth of semiconductor substrate 310 exposed in recess 322 is in arange of about 10 to 100 nm. Silicon epitaxial growth layer 330 includesan undoped silicon layer. The selective epitaxial process for formingsilicon epitaxial silicon growth layer 330 is performed by a thermaltreatment process. The thermal treatment process is performed under a H₂atmosphere at a temperature in a range of about 500° C. to 1,000° C. Aplasma cleaning process including SF₆/H₂ is performed on the etchedsemiconductor substrate 310. The plasma cleaning process and the thermaltreatment process are performed by an in-situ method.

In one embodiment, in the vertical direction, the line width of siliconepitaxial growth layer 330 is F, and the line width of semiconductorsubstrate 310 in second active region 108 is G (where 7F/20<G<19F/20 andF is a distance between the neighboring two gates).

Referring to FIG. 3 e, a second insulating film for device isolation 318is formed over semiconductor substrate 310 to fill trench 314. Secondinsulating film for device isolation 318 is polished (or removed) untilsilicon epitaxial growth layer 330 is exposed, to form a deviceisolation structure 320. Device isolation structure 320 has a stackedstructure including first insulating film for device isolation 316 andsecond insulating film for device isolation 318.

Referring to FIG. 3 f, a hard mask layer 332 is formed oversemiconductor substrate 310. A photoresist film (not shown) is formedover hard mask layer 332. The photoresist film is exposed and developedusing a mask (not shown) that defines fin gate region 102 of FIG. 1, toform a photoresist pattern 334. Hard mask layer 332 and a portion ofdevice isolation structure 320 are selectively etched using photoresistpattern 334 as a mask, to form a fin gate recess 336 that exposes a fintype active region 338.

Referring to FIGS. 3 g and 3 h, hard mask layer 332 and photoresistpattern 334 are removed to expose semiconductor substrate 310 and asurface of fin type active region 338. A gate insulating film 340 isformed over semiconductor substrate 310 and a surface of fin type activeregion 338. A lower gate conductive layer 350 is formed over gateinsulating film 340 to fill fin gate recess 336. An upper gateconductive layer 360 and a gate hard mask layer 370 are formed overlower gate conductive layer 350. Gate hard mask layer 370, upper gateconductive layer 360 and lower gate conductive layer 350 are patternedusing a gate mask (not shown) to form a fin gate structure 380 having astacked structure including a gate hard mask pattern 372, an upper gateelectrode 362 and a lower gate electrode 352.

FIG. 4 is a cross-sectional view illustrating a method for fabricating asemiconductor device according to an embodiment of the invention. Aselective epitaxial process is performed on a semiconductor substrate410 exposed in recess 322 of FIG. 3 c as a seed layer, to form a siliconepitaxial growth layer 430. A pad insulating film 412 is disposed oversemiconductor substrate 410 in second active region 108 of FIG. 1, sothat silicon epitaxial growth layer 430 is not formed.

Silicon epitaxial growth layer 430 is formed of an impurity dopedsilicon layer. In one implementation, the impurity of silicon epitaxialgrowth layer 430 is selected from the group of consisting of B, BF₂, As,P, and combinations thereof. In other implementations, the impurity ofsilicon epitaxial growth layer 430 may be selected from other groups.Impurity doping concentration is in a range of about 1E18 ions/cm² to5E20 ions/cm². The impurity doping concentration required for siliconepitaxial growth layer 430 is not limited.

As described above, in a semiconductor device and a method forfabricating the same according to an embodiment of the invention, asecond active region (or source/drains) is formed of a silicon epitaxialgrowth layer. In the vertical direction, a line width of a second activeregion (or a gate region) is formed to be smaller than the width of afirst active region, thereby improving short channel effects such asDIBL. In a device isolation structure, an initial interval between theactive regions becomes broader to increase a gap-fill margin.

The above embodiments of the invention are illustrative and notlimitative. Various alternatives and equivalents are possible. Theinvention is not limited by the type of deposition, etching polishing,and patterning steps described herein. Nor is the invention limited toany specific type of semiconductor device. For example, the presentinvention may be implemented in a dynamic random access memory (DRAM)device or non volatile memory device. Other additions, subtractions, ormodifications are obvious in view of the present disclosure and areintended to fall within the scope of the appended claims.

1. A semiconductor device comprising: an active region including asource/drain and a gate; and a device isolation region defining theactive region, wherein the gate is formed as a portion of a fin gate,and the source/drain is an epitaxial layer formed between theneighboring gates as a seed layer, wherein in a longitudinal directionof the gate, a line width of the source/drain is greater than the widthof the gate.
 2. The semiconductor device of claim 1, wherein in alongitudinal direction of the gate, the line width of the source/drainis F, and the line width of the gate region is G, where 7F/20<G<19F/20.